Glass interposers and glass core substrates are being pursued intensively by leading device makers, materials suppliers, and equipment vendors for advanced packaging applications, as discussed in IDTechEx's brand‑new report "Glass in Semiconductors 2026-2036: Applications, Emerging Technologies, and Market Insights".
Global activity sets the stage
Intel has publicly demonstrated its glass core substrates for next-generation advanced packaging, positioning the work as foundational research for the latter part of this decade rather than imminent high‑volume manufacturing, which helps frame expectations for the technology's maturity today.
In parallel, Absolics, an affiliate of SKC, has secured preliminary U.S. CHIPS Act support to stand up a glass‑substrate facility in Georgia, signaling real capital formation while still implying multi‑year ramps before meaningful production validation. Materials suppliers such as SCHOTT and AGC are aligning portfolios and programs around low‑coefficient‑of‑thermal‑expansion (CTE) glass and packaging‑grade formats, indicating upstream readiness to support trials and early adoption phases.
Why glass
For artificial intelligence (AI) and high‑performance computing (HPC), package footprints, signal counts, and power delivery demands stress organic laminates on warpage, via pitch, and dielectric loss, whereas glass offers flatness, dimensional stability, and low loss favorable to high‑speed signaling and large‑format integration.
That said, silicon interposers already provide fine redistribution with true vertical interconnection via through‑silicon vias (TSVs), and at present both silicon and glass carry high-cost structures, making any transition contingent on proving yield, reliability, and end‑to‑end cost at system scale rather than on material properties alone. The prudent view is that glass interposers and glass core substrates are being actively pursued by credible players, but success remains to be earned in manufacturing and economics, not presumed by roadmap slides.
TGV manufacturing: necessary condition, not a foregone conclusion
Through‑glass vias (TGVs) underpin vertical power and signal paths in glass, typically formed by processes such as laser‑assisted drilling and wet etch, then metallized by full copper fill or sidewall plating with dielectric infill, each bringing distinct stress, planarity, and reliability trade‑offs.
High‑volume viability depends on repeatable control of via geometry, seed coverage in reentrant sections, void‑free metal deposition, chemical‑mechanical planarization budgets, and crack suppression during thermal cycling in thin panels, together with high‑speed, 100% in‑line inspection capable of covering panels that can contain over a million vias to prevent undetected "killer" defects from escaping into downstream steps.
Progress has been steady across drilling physics, plating chemistries, and metrology, but the industry is still converging on stable, transferable process windows that remain robust under production variability.
Panel‑level processing: promise that must be earned by yield
Panel‑level packaging (PLP) draws on display‑class handling to fabricate many interposers or cores per panel, with ecosystems coalescing around sizes from roughly 310 × 310 mm up to the 515 × 510 mm class, aiming to amortize lithography and metallization across more units.
For glass, the panel case is particularly compelling because flatness and stiffness aid overlay and coplanarity on large formats, yet cost relief arrives only when fragile‑edge handling, warpage control, and defectivity are mastered at throughput, not merely because the panel is larger. In short, PLP is a lever that can lower cost per package, but it unlocks only after yield learning closes the gap between pilot demonstrations and stable factory practice.
Architectural fit: where glass could matter most first
Package architects seeking to co‑locate large dies or chiplets with dense high‑speed I/O and robust power delivery networks (PDNs) can benefit from glass's low dielectric loss and mechanical stability, which together support long‑reach redistribution and fine‑pitch assembly on large substrates.
These traits are particularly relevant for reticle‑scale logic, switch application‑specific integrated circuits (ASICs), and accelerator modules that need thousands of I/O bumps and tight noise budgets, provided the manufacturing stack proves reliable and cost‑competitive at target volumes. Near‑term deployments are therefore most plausible in designs where organic limits are most constraining and where silicon interposers' cost and size ceilings pinch, creating an opening for glass if panel economics materialize.
Supply chain shifts: tools, standards, and regionalization
Commercializing glass at scale extends beyond glass furnaces to include laser drilling, wet chemistries, seed/barrier stacks, electroplating, chemical‑mechanical planarization (CMP), multilayer redistribution layer (RDL) lithography, and in‑line inspection, all tuned for panels rather than wafers. This invites convergence between printed circuit board (PCB), display, and outsourced semiconductor assembly and test (OSAT) competencies, while public funding, such as the CHIPS Act support for Absolics, nudges regional capacity and risk diversification in advanced packaging.
As factories stabilize around panel formats and process flows, standardization in panel sizes, carriers, and test vehicles can accelerate learning curves and reduce cost‑of‑quality across the ecosystem.
Conclusion
Glass interposers and glass core substrates are being actively pursued for advanced packaging in AI and HPC, offering flatness, dimensional stability, and low dielectric loss, but the decisive hurdles remain including yield, TGV reliability, and PLP cost at production scale. Near‑term insertion will depend on sustained process windows across drilling, metallization, and planarization, as well as validated RDL performance on large panels that meet system‑level power‑delivery and high‑speed signaling targets at acceptable total cost of ownership.
For comprehensive analysis of technology pathways, the strategies and trends, and market sizing with 2026-2036 forecasts, see IDTechEx's brand‑new report "Glass in Semiconductors 2026-2036: Applications, Emerging Technologies, and Market Insights".
For more information on this report, including downloadable sample pages, please visit www.IDTechEx.com/GlassinSC, or for the full portfolio of semiconductor research available from IDTechEx, see www.IDTechEx.com/Research/Semiconductors.
